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added cpu_info and fui

master
Felix Brendel 5 anos atrás
pai
0488aa91c9
commit
f54fdcbfac
8 arquivos alterados com 621 adições e 16 exclusões
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  1. +362
    -0
      cpu_info.hpp
  2. +6
    -6
      macros.hpp
  3. +0
    -0
      tests/build.bat
  4. +5
    -2
      tests/build.sh
  5. BIN
     
  6. +240
    -0
      tests/cpu_info.cpp
  7. BIN
     
  8. +8
    -8
      tests/main.cpp

+ 362
- 0
cpu_info.hpp Ver arquivo

@@ -0,0 +1,362 @@
#pragma once
#include <string.h>

#ifdef MSVC
#include <immintrin.h>
#define platform_independent_cpuid(function_id, array_of_registers) \
__cpuid(array_of_registers, function_id)

#define platform_independent_cpuidex(function_id, sub_function_id, array_of_registers) \
__cpuid_count(array_of_registers, function_id, sub_function_id)
#else
#include <cpuid.h>
#define platform_independent_cpuid(function_id, array_of_registers) \
__cpuid(function_id, array_of_registers[0], array_of_registers[1], \
array_of_registers[2],array_of_registers[3])

#define platform_independent_cpuidex(function_id, sub_function_id, array_of_registers) \
__cpuid_count (function_id, sub_function_id, array_of_registers[0], \
array_of_registers[1], array_of_registers[2], \
array_of_registers[3])
#endif



enum struct Edx_1_Feature_Flags {
fpu = 1<<0, // Onboard x87 FPU
vme = 1<<1, // Virtual 8086 mode extensions (such as VIF, VIP, PIV)
de = 1<<2, // Debugging extensions (CR4 bit 3)
pse = 1<<3, // Page Size Extension
tsc = 1<<4, // Time Stamp Counter
msr = 1<<5, // Model-specific registers
pae = 1<<6, // Physical Address Extension
mce = 1<<7, // Machine Check Exception
cx8 = 1<<8, // CMPXCHG8 (compare-and-swap) instruction
apic = 1<<9, // Onboard Advanced Programmable Interrupt Controller
_resv1 = 1<<10, // (reserved)
sep = 1<<11, // SYSENTER and SYSEXIT instructions
mtrr = 1<<12, // Memory Type Range Registers
pge = 1<<13, // Page Global Enable bit in CR4
mca = 1<<14, // Machine check architecture
cmov = 1<<15, // Conditional move and FCMOV instructions
pat = 1<<16, // Page Attribute Table
pse_36 = 1<<17, // 36-bit page size extension
psn = 1<<18, // Processor Serial Number
clfsh = 1<<19, // CLFLUSH instruction (SSE2)
_resv2 = 1<<20, // (reserved)
ds = 1<<21, // Debug store: save trace of executed jumps
acpi = 1<<22, // Onboard thermal control MSRs for ACPI
mmx = 1<<23, // MMX instructions
fxsr = 1<<24, // FXSAVE, FXRESTOR instructions, CR4 bit 9
sse = 1<<25, // SSE instructions (a.k.a. Katmai New Instructions)
sse2 = 1<<26, // SSE2 instructions
ss = 1<<27, // CPU cache implements self-snoop
htt = 1<<28, // Hyper-threading
tm = 1<<29, // Thermal monitor automatically limits temperature
ia64 = 1<<30, // IA64 processor emulating x86
pbe = 1<<31, // Pending Break Enable (PBE# pin) wakeup capability
};

enum struct Ecx_1_Feature_Flags {
sse3 = 1<<0, // Prescott New Instructions-SSE3 (PNI)
pclmulqdq = 1<<1, // PCLMULQDQ
dtes64 = 1<<2, // 64-bit debug store (edx bit 21)
monitor = 1<<3, // MONITOR and MWAIT instructions (SSE3)
ds_cpl = 1<<4, // CPL qualified debug store
vmx = 1<<5, // Virtual Machine eXtensions
smx = 1<<6, // Safer Mode Extensions (LaGrande)
est = 1<<7, // Enhanced SpeedStep
tm2 = 1<<8, // Thermal Monitor 2
ssse3 = 1<<9, // Supplemental SSE3 instructions
cnxt_id = 1<<10, // L1 Context ID
sdbg = 1<<11, // Silicon Debug interface
fma = 1<<12, // Fused multiply-add (FMA3)
cx16 = 1<<13, // CMPXCHG16B instruction
xtpr = 1<<14, // Can disable sending task priority messages
pdcm = 1<<15, // Perfmon & debug capability
_resv1 = 1<<16, // (reserved)
pcid = 1<<17, // Process context identifiers (CR4 bit 17)
dca = 1<<18, // Direct cache access for DMA writes
sse4_1 = 1<<19, // SSE4.1 instructions
sse4_2 = 1<<20, // SSE4.2 instructions
x2apic = 1<<21, // x2APIC
movbe = 1<<22, // MOVBE instruction (big-endian)
popcnt = 1<<23, // POPCNT instruction
tsc_deadline = 1<<24, // APIC implements one-shot operation using a TSC deadline value
aes = 1<<25, // AES instruction set
xsave = 1<<26, // XSAVE, XRESTOR, XSETBV, XGETBV
osxsave = 1<<27, // XSAVE enabled by OS
avx = 1<<28, // Advanced Vector Extensions
f16c = 1<<29, // F16C (half-precision) FP feature
rdrnd = 1<<30, // RDRAND (on-chip random number generator) feature
hypervisor = 1<<31, // Hypervisor present (always zero on physical CPUs)
};

enum struct Ebx_7_Extended_Feature_Flags {
fsgsbase = 1<<0, // Access to base of %fs and %gs
_idk1 = 1<<1, //
sgx = 1<<2, // Software Guard Extensions
bmi1 = 1<<3, // Bit Manipulation Instruction Set 1
hle = 1<<4, // TSX Hardware Lock Elision
avx2 = 1<<5, // Advanced Vector Extensions 2
_idk2 = 1<<6, //
smep = 1<<7, // Supervisor Mode Execution Prevention
bmi2 = 1<<8, // Bit Manipulation Instruction Set 2
erms = 1<<9, // Enhanced REP MOVSB/STOSB
invpcid = 1<<10, // INVPCID instruction
rtm = 1<<11, // TSX Restricted Transactional Memory
pqm = 1<<12, // Platform Quality of Service Monitoring
_idk3 = 1<<13, //
mpx = 1<<14, // Intel MPX (Memory Protection Extensions)
pqe = 1<<15, // Platform Quality of Service Enforcement
avx512_f = 1<<16, // AVX-512 Foundation
avx512_dq = 1<<17, // AVX-512 Doubleword and Quadword Instructions
rdseed = 1<<18, // RDSEED instruction
adx = 1<<19, // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
smap = 1<<20, // Supervisor Mode Access Prevention
avx512_ifma = 1<<21, // AVX-512 Integer Fused Multiply-Add Instructions
pcommit = 1<<22, // PCOMMIT instruction
clflushopt = 1<<23, // CLFLUSHOPT instruction
clwb = 1<<24, // CLWB instruction
intel_pt = 1<<25, // Intel Processor Trace
avx512_pf = 1<<26, // AVX-512 Prefetch Instructions
avx512_er = 1<<27, // AVX-512 Exponential and Reciprocal Instructions
avx512_cd = 1<<28, // AVX-512 Conflict Detection Instructions
sha = 1<<29, // Intel SHA extensions
avx512_bw = 1<<30, // AVX-512 Byte and Word Instructions
avx512_vl = 1<<31, // AVX-512 Vector Length Extensions
};

enum struct Ecx_7_Extended_Feature_Flags {
prefetchwt1 = 1<<0, // PREFETCHWT1 instruction
avx512_vbmi = 1<<1, // AVX-512 Vector Bit Manipulation Instructions
umip = 1<<2, // User-mode Instruction Prevention
pku = 1<<3, // Memory Protection Keys for User-mode pages
ospke = 1<<4, // PKU enabled by OS
waitpkg = 1<<5, // Timed pause and user-level monitor/wait
avx512_vbmi2 = 1<<6, // AVX-512 Vector Bit Manipulation Instructions 2
cet_ss = 1<<7, // Control flow enforcement (CET) shadow stack
gfni = 1<<8, // Galois Field instructions
vaes = 1<<9, // Vector AES instruction set (VEX-256/EVEX)
vpclmulqdq = 1<<10, // CLMUL instruction set (VEX-256/EVEX)
avx512_vnni = 1<<11, // AVX-512 Vector Neural Network Instructions
avx512_bitalg = 1<<12, // AVX-512 BITALG instructions
_resv1 = 1<<13, // (reserved)
avx512_vpopcntdq = 1<<14, // AVX-512 Vector Population Count Double and Quad-word
_resv2 = 1<<15, // (reserved)
intel_5lp = 1<<16, // 5-level paging
mawau1 = 1<<17, // The value of userspace MPX Address-Width Adjust used ...
mawau2 = 1<<18, // ... by the BNDLDX and BNDSTX Intel MPX instructions ...
mawau3 = 1<<19, // ... in 64-bit mode
mawau4 = 1<<20, //
mawau5 = 1<<21, //
rdpid = 1<<22, // Read Processor ID and IA32_TSC_AUX
_resv3 = 1<<23, // (reserved)
_resv4 = 1<<24, // (reserved)
cldemote = 1<<25, // Cache line demote
_resv5 = 1<<26, // (reserved)
movdiri = 1<<27, //
movdir64b = 1<<28, //
enqcmd = 1<<29, // Enqueue Stores
sgx_lc = 1<<30, // SGX Launch Configuration
pks = 1<<31, // Protection keys for supervisor-mode pages
};

enum struct Edx_7_Extended_Feature_Flags {
_resv1 = 1<<0, // (reserved)
_resv2 = 1<<1, // (reserved)
avx512_4vnniw = 1<<2, // AVX-512 4-register Neural Network Instructions
avx512_4fmaps = 1<<3, // AVX-512 4-register Multiply Accumulation Single precision
fsrm = 1<<4, // Fast Short REP MOVSB
_resv3 = 1<<5, // (reserved)
_resv4 = 1<<6, // (reserved)
_resv5 = 1<<7, // (reserved)
avx512_vp2intersect = 1<<8, // AVX-512 VP2INTERSECT Doubleword and Quadword Instructions
SRBDS_CTRL = 1<<9, // Special Register Buffer Data Sampling Mitigations
md_clear = 1<<10, // VERW instruction clears CPU buffers
_resv6 = 1<<11, // (reserved)
_resv7 = 1<<12, // (reserved)
tsx_force_abort = 1<<13, //
serialize = 1<<14, // Serialize instruction execution
hybrid = 1<<15, //
TSXLDTRK = 1<<16, // TSX suspend load address tracking
_resv8 = 1<<17, // (reserved)
pconfig = 1<<18, // Platform configuration (Memory Encryption Technologies Instructions)
lbr = 1<<19, // Architectural Last Branch Records
cet_ibt = 1<<20, // Control flow enforcement (CET) indirect branch tracking
_resv9 = 1<<21, // (reserved)
amx_bf16 = 1<<22, // Tile computation on bfloat16 numbers
_resv10 = 1<<23, // (reserved)
amx_tile = 1<<24, // Tile architecture
amx_int8 = 1<<25, // Tile computation on 8-bit integers
spec_ctrl = 1<<26,
// Speculation Control, part of Indirect Branch Control (IBC):
// Indirect Branch Restricted Speculation (IBRS) and
// Indirect Branch Prediction Barrier (IBPB)
stibp = 1<<27, // Single Thread Indirect Branch Predictor, part of IBC
l1d_flush = 1<<28, // IA32_FLUSH_CMD MSR
ia32_arch_capabilities = 1<<29, // Speculative Side Channel Mitigations
ia32_core_capabilities = 1<<30, // Support for a MSR listing model-specific core capabilities
ssbd = 1<<31, // Speculative Store Bypass Disable, as mitigation for Speculative Store Bypass (IA32_SPEC_CTRL)
};

// NOTE(Felix): Left out flags are duplicates from Edx_1_Feature_Flags
enum struct Edx_81_Extended_Feature_Flags {
syscall = 1<<11, // SYSCALL and SYSRET instructions
mp = 1<<19, // Multiprocessor Capable
nx = 1<<20, // NX (no-execute) bit
mmxext = 1<<22, // Extended MMX
fxsr_opt = 1<<25, // FXSAVE/FXRSTOR optimizations
pdpe1gb = 1<<26, // Gibibyte pages
rdtscp = 1<<27, // RDTSCP instruction
l1d_flush = 1<<28, // IA32_FLUSH_CMD MSR
lm = 1<<29, // Long mode
_3dnowext = 1<<30, // Extended 3DNow!
_3dnow = 1<<31, // 3DNow!
};

enum struct Ecx_81_Extended_Feature_Flags {
lahf_lm = 1<<0, // LAHF/SAHF in long mode
cmp_legacy = 1<<1, // Hyperthreading not valid
svm = 1<<2, // Secure Virtual Machine
extapic = 1<<3, // Extended APIC space
cr8_legacy = 1<<4, // CR8 in 32-bit mode
abm = 1<<5, // Advanced bit manipulation (lzcnt and popcnt)
sse4a = 1<<6, // SSE4a
misalignsse = 1<<7, // Misaligned SSE mode
_3dnowprefetch= 1<<8, // PREFETCH and PREFETCHW instructions
osvw = 1<<9, // OS Visible Workaround
ibs = 1<<10, // Instruction Based Sampling
xop = 1<<11, // XOP instruction set
skinit = 1<<12, // SKINIT/STGI instructions
wdt = 1<<13, // Watchdog timer
_resv1 = 1<<14, // (reserved)
lwp = 1<<15, // Light Weight Profiling
fma4 = 1<<16, // 4 operands fused multiply-add
tce = 1<<17, // Translation Cache Extension
_resv2 = 1<<18, // (reserved)
nodeid_msr = 1<<19, // NodeID MSR
_resv3 = 1<<20, // (reserved)
tbm = 1<<21, // Trailing Bit Manipulation
topoext = 1<<22, // opology Extensions
perfctr_core = 1<<23, // Core performance counter extensions
perfctr_nb = 1<<24, // NB performance counter extensions
_resv4 = 1<<25, // (reserved)
dbx = 1<<26, // Data breakpoint extensions
perftsc = 1<<27, // Performance TSC
pcx_l2i = 1<<28, // L2I perf counter extensions
_resv5 = 1<<29, // (reserved)
_resv6 = 1<<30, // (reserved)
_resv7 = 1<<31, // (reserved)
};

struct Cpu_Info {
char vendor[0x20];
char brand[0x40];

bool is_intel;
bool is_amd;

int f_1_ECX;
int f_1_EDX;
int f_7_EBX;
int f_7_ECX;
int f_7_EDX;
int f_81_ECX;
int f_81_EDX;
};

inline auto query_cpu_feature(Cpu_Info* info, Edx_1_Feature_Flags flag) -> bool {
return info->f_1_EDX & (int)flag;
}

inline auto query_cpu_feature(Cpu_Info* info, Ecx_1_Feature_Flags flag) -> bool {
return info->f_1_ECX & (int)flag;
}

inline auto query_cpu_feature(Cpu_Info* info, Ebx_7_Extended_Feature_Flags flag) -> bool {
return info->f_7_EBX & (int)flag;
}

inline auto query_cpu_feature(Cpu_Info* info, Ecx_7_Extended_Feature_Flags flag) -> bool {
return info->f_7_ECX & (int)flag;
}

inline auto query_cpu_feature(Cpu_Info* info, Edx_7_Extended_Feature_Flags flag) -> bool {
return info->f_7_EDX & (int)flag;
}

inline auto query_cpu_feature(Cpu_Info* info, Edx_81_Extended_Feature_Flags flag) -> bool {
return info->f_81_EDX & (int)flag;
}

inline auto query_cpu_feature(Cpu_Info* info, Ecx_81_Extended_Feature_Flags flag) -> bool {
return info->f_81_ECX & (int)flag;
}

auto get_cpu_info(Cpu_Info* info) -> void {
*info = {};

int nIds_ = 0;
int nExIds_ = 0;

int register_sets[3][4];

info->is_intel = false;
info->is_amd = false;

// Calling __cpuid with 0x0 as the function_id argument
// gets the number of the highest valid function ID.
platform_independent_cpuid(0, register_sets[0]);
nIds_ = register_sets[0][0];

// Capture vendor string
memset(info->vendor, 0, sizeof(info->vendor));
memcpy(info->vendor + 0, register_sets[0]+1, sizeof(int));
memcpy(info->vendor + 4, register_sets[0]+3, sizeof(int));
memcpy(info->vendor + 8, register_sets[0]+2, sizeof(int));

if (strcmp(info->vendor, "GenuineIntel") == 0) {
info->is_intel = true;
} else if (strcmp(info->vendor, "AuthenticAMD") == 0) {
info->is_amd = true;
}

if (nIds_ >= 1) {
platform_independent_cpuidex(1, 0, register_sets[0]);
info->f_1_ECX = register_sets[0][2];
info->f_1_EDX = register_sets[0][3];

if (nIds_ >= 7) {
platform_independent_cpuidex(7, 0, register_sets[1]);
info->f_7_EBX = register_sets[1][1];
info->f_7_ECX = register_sets[1][2];
info->f_7_EDX = register_sets[1][3];
}
}

// Calling __cpuid with 0x80000000 as the function_id argument
// gets the number of the highest valid extended ID.
platform_independent_cpuid(0x80000000, register_sets[2]);
nExIds_ = register_sets[2][0];

memset(info->brand, 0, sizeof(info->brand));

// load bitset with flags for function 0x80000001
if (nExIds_ >= 0x80000001) {
platform_independent_cpuidex(0x80000001, 0, register_sets[2]);
info->f_81_ECX = register_sets[2][2];
info->f_81_EDX = register_sets[2][3];

// Interpret CPU brand string if reported
if (nExIds_ >= 0x80000004) {
platform_independent_cpuidex(0x80000002, 0, register_sets[0]);
platform_independent_cpuidex(0x80000003, 0, register_sets[1]);
platform_independent_cpuidex(0x80000004, 0, register_sets[2]);

memcpy(info->brand + 0, register_sets[0], sizeof(register_sets[0]));
memcpy(info->brand + 16, register_sets[1], sizeof(register_sets[1]));
memcpy(info->brand + 32, register_sets[2], sizeof(register_sets[2]));
}
}
}

+ 6
- 6
macros.hpp Ver arquivo

@@ -6,12 +6,12 @@
#define label(x, y) concat(x, y)
#define line_label(x) label(x, __LINE__)

#ifndef min
#define min(a, b) ((a) < (b)) ? (a) : (b)
#endif
#ifndef max
#define max(a, b) ((a) > (b)) ? (a) : (b)
#endif
// #ifndef min
// #define min(a, b) ((a) < (b)) ? (a) : (b)
// #endif
// #ifndef max
// #define max(a, b) ((a) > (b)) ? (a) : (b)
// #endif

/**
* Defer *


build.bat → tests/build.bat Ver arquivo


build.sh → tests/build.sh Ver arquivo

@@ -4,10 +4,13 @@ pushd $SCRIPTPATH > /dev/null

# _DEBUG
# time g++ -fpermissive src/main.cpp -g -o ./bin/slime --std=c++17 || exit 1
time clang++ -D_DEBUG -D_PROFILING -fpermissive test.cpp -g -o ./ftb --std=c++17 || exit 1
time clang++ -D_DEBUG -D_PROFILING -fpermissive main.cpp -g -o ./ftb --std=c++17 || exit 1
time clang++ -D_DEBUG -D_PROFILING -fpermissive cpu_info.cpp -g -o ./cpu_info --std=c++17 || exit 1

echo ""
time valgrind --leak-check=full ./ftb
# time valgrind --leak-check=full ./ftb
time ./ftb
time ./cpu_info

popd > /dev/null
unset TIMEFORMAT

BIN
Ver arquivo


+ 240
- 0
tests/cpu_info.cpp Ver arquivo

@@ -0,0 +1,240 @@
#include <stdio.h>
#include "../cpu_info.hpp"

auto print_full_cpu_info() -> void {
Cpu_Info info;
get_cpu_info(&info);
printf("-------------------\n");
printf(" CPU INFO \n");
printf("-------------------\n");
printf("vendor: %s\n", info.vendor);
printf("brand: %s\n", info.brand);
printf("-------------------\n");
printf("Edx_1_Feature_Flags\n");
printf("-------------------\n");
printf("fpu: %s // Onboard x87 FPU\n", query_cpu_feature(&info, Edx_1_Feature_Flags::fpu) ? "yes" : "no ");
printf("vme: %s // Virtual 8086 mode extensions (such as VIF, VIP, PIV)\n", query_cpu_feature(&info, Edx_1_Feature_Flags::vme) ? "yes" : "no ");
printf("de: %s // Debugging extensions (CR4 bit 3)\n", query_cpu_feature(&info, Edx_1_Feature_Flags::de) ? "yes" : "no ");
printf("pse: %s // Page Size Extension\n", query_cpu_feature(&info, Edx_1_Feature_Flags::pse) ? "yes" : "no ");
printf("tsc: %s // Time Stamp Counter\n", query_cpu_feature(&info, Edx_1_Feature_Flags::tsc) ? "yes" : "no ");
printf("msr: %s // Model-specific registers\n", query_cpu_feature(&info, Edx_1_Feature_Flags::msr) ? "yes" : "no ");
printf("pae: %s // Physical Address Extension\n", query_cpu_feature(&info, Edx_1_Feature_Flags::pae) ? "yes" : "no ");
printf("mce: %s // Machine Check Exception\n", query_cpu_feature(&info, Edx_1_Feature_Flags::mce) ? "yes" : "no ");
printf("cx8: %s // CMPXCHG8 (compare-and-swap) instruction\n", query_cpu_feature(&info, Edx_1_Feature_Flags::cx8) ? "yes" : "no ");
printf("apic: %s // Onboard Advanced Programmable Interrupt Controller\n", query_cpu_feature(&info, Edx_1_Feature_Flags::apic) ? "yes" : "no ");
printf("_resv1: %s // (reserved)\n", query_cpu_feature(&info, Edx_1_Feature_Flags::_resv1) ? "yes" : "no ");
printf("sep: %s // SYSENTER and SYSEXIT instructions\n", query_cpu_feature(&info, Edx_1_Feature_Flags::sep) ? "yes" : "no ");
printf("mtrr: %s // Memory Type Range Registers\n", query_cpu_feature(&info, Edx_1_Feature_Flags::mtrr) ? "yes" : "no ");
printf("pge: %s // Page Global Enable bit in CR4\n", query_cpu_feature(&info, Edx_1_Feature_Flags::pge) ? "yes" : "no ");
printf("mca: %s // Machine check architecture\n", query_cpu_feature(&info, Edx_1_Feature_Flags::mca) ? "yes" : "no ");
printf("cmov: %s // Conditional move and FCMOV instructions\n", query_cpu_feature(&info, Edx_1_Feature_Flags::cmov) ? "yes" : "no ");
printf("pat: %s // Page Attribute Table\n", query_cpu_feature(&info, Edx_1_Feature_Flags::pat) ? "yes" : "no ");
printf("pse_36: %s // 36-bit page size extension\n", query_cpu_feature(&info, Edx_1_Feature_Flags::pse_36) ? "yes" : "no ");
printf("psn: %s // Processor Serial Number\n", query_cpu_feature(&info, Edx_1_Feature_Flags::psn) ? "yes" : "no ");
printf("clfsh: %s // CLFLUSH instruction (SSE2)\n", query_cpu_feature(&info, Edx_1_Feature_Flags::clfsh) ? "yes" : "no ");
printf("_resv2: %s // (reserved)\n", query_cpu_feature(&info, Edx_1_Feature_Flags::_resv2) ? "yes" : "no ");
printf("ds: %s // Debug store: save trace of executed jumps\n", query_cpu_feature(&info, Edx_1_Feature_Flags::ds) ? "yes" : "no ");
printf("acpi: %s // Onboard thermal control MSRs for ACPI\n", query_cpu_feature(&info, Edx_1_Feature_Flags::acpi) ? "yes" : "no ");
printf("mmx: %s // MMX instructions\n", query_cpu_feature(&info, Edx_1_Feature_Flags::mmx) ? "yes" : "no ");
printf("fxsr: %s // FXSAVE, FXRESTOR instructions, CR4 bit 9\n", query_cpu_feature(&info, Edx_1_Feature_Flags::fxsr) ? "yes" : "no ");
printf("sse: %s // SSE instructions (a.k.a. Katmai New Instructions)\n", query_cpu_feature(&info, Edx_1_Feature_Flags::sse) ? "yes" : "no ");
printf("sse2: %s // SSE2 instructions\n", query_cpu_feature(&info, Edx_1_Feature_Flags::sse2) ? "yes" : "no ");
printf("ss: %s // CPU cache implements self-snoop\n", query_cpu_feature(&info, Edx_1_Feature_Flags::ss) ? "yes" : "no ");
printf("htt: %s // Hyper-threading\n", query_cpu_feature(&info, Edx_1_Feature_Flags::htt) ? "yes" : "no ");
printf("tm: %s // Thermal monitor automatically limits temperature\n", query_cpu_feature(&info, Edx_1_Feature_Flags::tm) ? "yes" : "no ");
printf("ia64: %s // IA64 processor emulating x86\n", query_cpu_feature(&info, Edx_1_Feature_Flags::ia64) ? "yes" : "no ");
printf("pbe: %s // Pending Break Enable (PBE# pin) wakeup capability\n", query_cpu_feature(&info, Edx_1_Feature_Flags::pbe) ? "yes" : "no ");
printf("-------------------\n");
printf("Ecx_1_Feature_Flags\n");
printf("-------------------\n");
printf("sse3: %s // Prescott New Instructions-SSE3 (PNI)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::sse3) ? "yes" : "no ");
printf("pclmulqdq: %s // PCLMULQDQ\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::pclmulqdq) ? "yes" : "no ");
printf("dtes64: %s // 64-bit debug store (edx bit 21)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::dtes64) ? "yes" : "no ");
printf("monitor: %s // MONITOR and MWAIT instructions (SSE3)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::monitor) ? "yes" : "no ");
printf("ds_cpl: %s // CPL qualified debug store\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::ds_cpl) ? "yes" : "no ");
printf("vmx: %s // Virtual Machine eXtensions\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::vmx) ? "yes" : "no ");
printf("smx: %s // Safer Mode Extensions (LaGrande)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::smx) ? "yes" : "no ");
printf("est: %s // Enhanced SpeedStep\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::est) ? "yes" : "no ");
printf("tm2: %s // Thermal Monitor 2\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::tm2) ? "yes" : "no ");
printf("ssse3: %s // Supplemental SSE3 instructions\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::ssse3) ? "yes" : "no ");
printf("cnxt_id: %s // L1 Context ID\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::cnxt_id) ? "yes" : "no ");
printf("sdbg: %s // Silicon Debug interface\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::sdbg) ? "yes" : "no ");
printf("fma: %s // Fused multiply-add (FMA3)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::fma) ? "yes" : "no ");
printf("cx16: %s // CMPXCHG16B instruction\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::cx16) ? "yes" : "no ");
printf("xtpr: %s // Can disable sending task priority messages\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::xtpr) ? "yes" : "no ");
printf("pdcm: %s // Perfmon & debug capability\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::pdcm) ? "yes" : "no ");
printf("_resv1: %s // (reserved)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::_resv1) ? "yes" : "no ");
printf("pcid: %s // Process context identifiers (CR4 bit 17)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::pcid) ? "yes" : "no ");
printf("dca: %s // Direct cache access for DMA writes\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::dca) ? "yes" : "no ");
printf("sse4_1: %s // SSE4.1 instructions\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::sse4_1) ? "yes" : "no ");
printf("sse4_2: %s // SSE4.2 instructions\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::sse4_2) ? "yes" : "no ");
printf("x2apic: %s // x2APIC\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::x2apic) ? "yes" : "no ");
printf("movbe: %s // MOVBE instruction (big-endian)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::movbe) ? "yes" : "no ");
printf("popcnt: %s // POPCNT instruction\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::popcnt) ? "yes" : "no ");
printf("tsc_deadline: %s // APIC implements one-shot operation using a TSC deadline value\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::tsc_deadline) ? "yes" : "no ");
printf("aes: %s // AES instruction set\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::aes) ? "yes" : "no ");
printf("xsave: %s // XSAVE, XRESTOR, XSETBV, XGETBV\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::xsave) ? "yes" : "no ");
printf("osxsave: %s // XSAVE enabled by OS\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::osxsave) ? "yes" : "no ");
printf("avx: %s // Advanced Vector Extensions\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::avx) ? "yes" : "no ");
printf("f16c: %s // F16C (half-precision) FP feature\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::f16c) ? "yes" : "no ");
printf("rdrnd: %s // RDRAND (on-chip random number generator) feature\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::rdrnd) ? "yes" : "no ");
printf("hypervisor: %s // Hypervisor present (always zero on physical CPUs)\n", query_cpu_feature(&info, Ecx_1_Feature_Flags::hypervisor) ? "yes" : "no ");
printf("----------------------------\n");
printf("Ebx_7_Extended_Feature_Flags\n");
printf("----------------------------\n");
printf("fsgsbase: %s // Access to base of %%fs and %%gs\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::fsgsbase) ? "yes" : "no ");
printf("_idk1: %s //\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::_idk1) ? "yes" : "no ");
printf("sgx: %s // Software Guard Extensions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::sgx) ? "yes" : "no ");
printf("bmi1: %s // Bit Manipulation Instruction Set 1\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::bmi1) ? "yes" : "no ");
printf("hle: %s // TSX Hardware Lock Elision\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::hle) ? "yes" : "no ");
printf("avx2: %s // Advanced Vector Extensions 2\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx2) ? "yes" : "no ");
printf("_idk2: %s //\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::_idk2) ? "yes" : "no ");
printf("smep: %s // Supervisor Mode Execution Prevention\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::smep) ? "yes" : "no ");
printf("bmi2: %s // Bit Manipulation Instruction Set 2\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::bmi2) ? "yes" : "no ");
printf("erms: %s // Enhanced REP MOVSB/STOSB\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::erms) ? "yes" : "no ");
printf("invpcid: %s // INVPCID instruction\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::invpcid) ? "yes" : "no ");
printf("rtm: %s // TSX Restricted Transactional Memory\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::rtm) ? "yes" : "no ");
printf("pqm: %s // Platform Quality of Service Monitoring\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::pqm) ? "yes" : "no ");
printf("_idk3: %s //\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::_idk3) ? "yes" : "no ");
printf("mpx: %s // Intel MPX (Memory Protection Extensions)\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::mpx) ? "yes" : "no ");
printf("pqe: %s // Platform Quality of Service Enforcement\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::pqe) ? "yes" : "no ");
printf("avx512_f: %s // AVX-512 Foundation\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_f) ? "yes" : "no ");
printf("avx512_dq: %s // AVX-512 Doubleword and Quadword Instructions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_dq) ? "yes" : "no ");
printf("rdseed: %s // RDSEED instruction\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::rdseed) ? "yes" : "no ");
printf("adx: %s // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::adx) ? "yes" : "no ");
printf("smap: %s // Supervisor Mode Access Prevention\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::smap) ? "yes" : "no ");
printf("avx512_ifma: %s // AVX-512 Integer Fused Multiply-Add Instructions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_ifma) ? "yes" : "no ");
printf("pcommit: %s // PCOMMIT instruction\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::pcommit) ? "yes" : "no ");
printf("clflushopt: %s // CLFLUSHOPT instruction\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::clflushopt) ? "yes" : "no ");
printf("clwb: %s // CLWB instruction\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::clwb) ? "yes" : "no ");
printf("intel_pt: %s // Intel Processor Trace\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::intel_pt) ? "yes" : "no ");
printf("avx512_pf: %s // AVX-512 Prefetch Instructions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_pf) ? "yes" : "no ");
printf("avx512_er: %s // AVX-512 Exponential and Reciprocal Instructions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_er) ? "yes" : "no ");
printf("avx512_cd: %s // AVX-512 Conflict Detection Instructions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_cd) ? "yes" : "no ");
printf("sha: %s // Intel SHA extensions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::sha) ? "yes" : "no ");
printf("avx512_bw: %s // AVX-512 Byte and Word Instructions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_bw) ? "yes" : "no ");
printf("avx512_vl: %s // AVX-512 Vector Length Extensions\n", query_cpu_feature(&info, Ebx_7_Extended_Feature_Flags::avx512_vl) ? "yes" : "no ");
printf("----------------------------\n");
printf("Ecx_7_Extended_Feature_Flags\n");
printf("----------------------------\n");
printf("prefetchwt1: %s // PREFETCHWT1 instruction\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::prefetchwt1) ? "yes" : "no ");
printf("avx512_vbmi: %s // AVX-512 Vector Bit Manipulation Instructions\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::avx512_vbmi) ? "yes" : "no ");
printf("umip: %s // User-mode Instruction Prevention\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::umip) ? "yes" : "no ");
printf("pku: %s // Memory Protection Keys for User-mode pages\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::pku) ? "yes" : "no ");
printf("ospke: %s // PKU enabled by OS\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::ospke) ? "yes" : "no ");
printf("waitpkg: %s // Timed pause and user-level monitor/wait\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::waitpkg) ? "yes" : "no ");
printf("avx512_vbmi2: %s // AVX-512 Vector Bit Manipulation Instructions 2\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::avx512_vbmi2) ? "yes" : "no ");
printf("cet_ss: %s // Control flow enforcement (CET) shadow stack\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::cet_ss) ? "yes" : "no ");
printf("gfni: %s // Galois Field instructions\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::gfni) ? "yes" : "no ");
printf("vaes: %s // Vector AES instruction set (VEX-256/EVEX)\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::vaes) ? "yes" : "no ");
printf("vpclmulqdq: %s // CLMUL instruction set (VEX-256/EVEX)\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::vpclmulqdq) ? "yes" : "no ");
printf("avx512_vnni: %s // AVX-512 Vector Neural Network Instructions\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::avx512_vnni) ? "yes" : "no ");
printf("avx512_bitalg: %s // AVX-512 BITALG instructions\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::avx512_bitalg) ? "yes" : "no ");
printf("_resv1: %s // (reserved)\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::_resv1) ? "yes" : "no ");
printf("avx512_vpopcntdq: %s // AVX-512 Vector Population Count Double and Quad-word\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::avx512_vpopcntdq)? "yes" : "no ");
printf("_resv2: %s // (reserved)\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::_resv2) ? "yes" : "no ");
printf("intel_5lp: %s // 5-level paging\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::intel_5lp) ? "yes" : "no ");
printf("mawau1: %s // The value of userspace MPX Address-Width Adjust used ...\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::mawau1) ? "yes" : "no ");
printf("mawau2: %s // ... by the BNDLDX and BNDSTX Intel MPX instructions ...\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::mawau2) ? "yes" : "no ");
printf("mawau3: %s // ... in 64-bit mode\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::mawau3) ? "yes" : "no ");
printf("mawau4: %s //\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::mawau4) ? "yes" : "no ");
printf("mawau5: %s //\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::mawau5) ? "yes" : "no ");
printf("rdpid: %s // Read Processor ID and IA32_TSC_AUX\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::rdpid) ? "yes" : "no ");
printf("_resv3: %s // (reserved)\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::_resv3) ? "yes" : "no ");
printf("_resv4: %s // (reserved)\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::_resv4) ? "yes" : "no ");
printf("cldemote: %s // Cache line demote\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::cldemote) ? "yes" : "no ");
printf("_resv5: %s // (reserved)\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::_resv5) ? "yes" : "no ");
printf("movdiri: %s //\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::movdiri) ? "yes" : "no ");
printf("movdir64b: %s //\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::movdir64b) ? "yes" : "no ");
printf("enqcmd: %s // Enqueue Stores\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::enqcmd) ? "yes" : "no ");
printf("sgx_lc: %s // SGX Launch Configuration\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::sgx_lc) ? "yes" : "no ");
printf("pks: %s // Protection keys for supervisor-mode pages\n", query_cpu_feature(&info, Ecx_7_Extended_Feature_Flags::pks) ? "yes" : "no ");
printf("----------------------------\n");
printf("Edx_7_Extended_Feature_Flags\n");
printf("----------------------------\n");
printf("_resv1: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv1) ? "yes" : "no ");
printf("_resv2: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv2) ? "yes" : "no ");
printf("avx512_4vnniw: %s // AVX-512 4-register Neural Network Instructions\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::avx512_4vnniw) ? "yes" : "no ");
printf("avx512_4fmaps: %s // AVX-512 4-register Multiply Accumulation Single precision\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::avx512_4fmaps) ? "yes" : "no ");
printf("fsrm: %s // Fast Short REP MOVSB\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::fsrm) ? "yes" : "no ");
printf("_resv3: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv3) ? "yes" : "no ");
printf("_resv4: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv4) ? "yes" : "no ");
printf("_resv5: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv5) ? "yes" : "no ");
printf("avx512_vp2intersect: %s // AVX-512 VP2INTERSECT Doubleword and Quadword Instructions\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::avx512_vp2intersect) ? "yes" : "no ");
printf("SRBDS_CTRL: %s // Special Register Buffer Data Sampling Mitigations\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::SRBDS_CTRL) ? "yes" : "no ");
printf("md_clear: %s // VERW instruction clears CPU buffers\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::md_clear) ? "yes" : "no ");
printf("_resv6: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv6) ? "yes" : "no ");
printf("_resv7: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv7) ? "yes" : "no ");
printf("tsx_force_abort: %s //\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::tsx_force_abort) ? "yes" : "no ");
printf("serialize: %s // Serialize instruction execution\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::serialize) ? "yes" : "no ");
printf("hybrid: %s //\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::hybrid) ? "yes" : "no ");
printf("TSXLDTRK: %s // TSX suspend load address tracking\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::TSXLDTRK) ? "yes" : "no ");
printf("_resv8: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv8) ? "yes" : "no ");
printf("pconfig: %s // Platform configuration (Memory Encryption Technologies Instructions)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::pconfig) ? "yes" : "no ");
printf("lbr: %s // Architectural Last Branch Records\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::lbr) ? "yes" : "no ");
printf("cet_ibt: %s // Control flow enforcement (CET) indirect branch tracking\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::cet_ibt) ? "yes" : "no ");
printf("_resv9: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv9) ? "yes" : "no ");
printf("amx_bf16: %s // Tile computation on bfloat16 numbers\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::amx_bf16) ? "yes" : "no ");
printf("_resv10: %s // (reserved)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::_resv10) ? "yes" : "no ");
printf("amx_tile: %s // Tile architecture\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::amx_tile) ? "yes" : "no ");
printf("amx_int8: %s // Tile computation on 8-bit integers\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::amx_int8) ? "yes" : "no ");
printf("spec_ctrl: %s // Speculation Control, part of Indirect Branch Control (IBC): Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Prediction Barrier (IBPB)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::spec_ctrl) ? "yes" : "no ");
printf("stibp: %s // Single Thread Indirect Branch Predictor, part of IBC\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::stibp) ? "yes" : "no ");
printf("l1d_flush: %s // IA32_FLUSH_CMD MSR\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::l1d_flush) ? "yes" : "no ");
printf("ia32_arch_capabilities: %s // Speculative Side Channel Mitigations\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::ia32_arch_capabilities) ? "yes" : "no ");
printf("ia32_core_capabilities: %s // Support for a MSR listing model-specific core capabilities\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::ia32_core_capabilities) ? "yes" : "no ");
printf("ssbd: %s // Speculative Store Bypass Disable, as mitigation for Speculative Store Bypass (IA32_SPEC_CTRL)\n", query_cpu_feature(&info, Edx_7_Extended_Feature_Flags::ssbd) ? "yes" : "no ");
printf("-----------------------------\n");
printf("Ebx_81_Extended_Feature_Flags\n");
printf("-----------------------------\n");
printf("syscall: %s // SYSCALL and SYSRET instructions\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::syscall) ? "yes" : "no ");
printf("mp: %s // Multiprocessor Capable\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::mp) ? "yes" : "no ");
printf("nx: %s // NX (no-execute) bit\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::nx) ? "yes" : "no ");
printf("mmxext: %s // Extended MMX\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::mmxext) ? "yes" : "no ");
printf("fxsr_opt: %s // FXSAVE/FXRSTOR optimizations\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::fxsr_opt) ? "yes" : "no ");
printf("pdpe1gb: %s // Gibibyte pages\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::pdpe1gb) ? "yes" : "no ");
printf("rdtscp: %s // RDTSCP instruction\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::rdtscp) ? "yes" : "no ");
printf("l1d_flush: %s // IA32_FLUSH_CMD MSR\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::l1d_flush) ? "yes" : "no ");
printf("lm: %s // Long mode\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::lm) ? "yes" : "no ");
printf("_3dnowext: %s // Extended 3DNow!\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::_3dnowext) ? "yes" : "no ");
printf("_3dnow: %s // 3DNow!\n", query_cpu_feature(&info, Edx_81_Extended_Feature_Flags::_3dnow) ? "yes" : "no ");
printf("-----------------------------\n");
printf("Ecx_81_Extended_Feature_Flags\n");
printf("-----------------------------\n");
printf("lahf_lm: %s // LAHF/SAHF in long mode\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::lahf_lm) ? "yes" : "no ");
printf("cmp_legacy: %s // Hyperthreading not valid\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::cmp_legacy) ? "yes" : "no ");
printf("svm: %s // Secure Virtual Machine\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::svm) ? "yes" : "no ");
printf("extapic: %s // Extended APIC space\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::extapic) ? "yes" : "no ");
printf("cr8_legacy: %s // CR8 in 32-bit mode\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::cr8_legacy) ? "yes" : "no ");
printf("abm: %s // Advanced bit manipulation (lzcnt and popcnt)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::abm) ? "yes" : "no ");
printf("sse4a: %s // SSE4a\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::sse4a) ? "yes" : "no ");
printf("misalignsse: %s // Misaligned SSE mode\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::misalignsse) ? "yes" : "no ");
printf("_3dnowprefetch: %s // PREFETCH and PREFETCHW instructions\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_3dnowprefetch) ? "yes" : "no ");
printf("osvw: %s // OS Visible Workaround\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::osvw) ? "yes" : "no ");
printf("ibs: %s // Instruction Based Sampling\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::ibs) ? "yes" : "no ");
printf("xop: %s // XOP instruction set\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::xop) ? "yes" : "no ");
printf("skinit: %s // SKINIT/STGI instructions\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::skinit) ? "yes" : "no ");
printf("wdt: %s // Watchdog timer\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::wdt) ? "yes" : "no ");
printf("_resv1: %s // (reserved)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_resv1) ? "yes" : "no ");
printf("lwp: %s // Light Weight Profiling\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::lwp) ? "yes" : "no ");
printf("fma4: %s // 4 operands fused multiply-add\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::fma4) ? "yes" : "no ");
printf("tce: %s // Translation Cache Extension\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::tce) ? "yes" : "no ");
printf("_resv2: %s // (reserved)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_resv2) ? "yes" : "no ");
printf("nodeid_msr: %s // NodeID MSR\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::nodeid_msr) ? "yes" : "no ");
printf("_resv3: %s // (reserved)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_resv3) ? "yes" : "no ");
printf("tbm: %s // Trailing Bit Manipulation\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::tbm) ? "yes" : "no ");
printf("topoext: %s // opology Extensions\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::topoext) ? "yes" : "no ");
printf("perfctr_core: %s // Core performance counter extensions\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::perfctr_core) ? "yes" : "no ");
printf("perfctr_nb: %s // NB performance counter extensions\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::perfctr_nb) ? "yes" : "no ");
printf("_resv4: %s // (reserved)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_resv4) ? "yes" : "no ");
printf("dbx: %s // Data breakpoint extensions\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::dbx) ? "yes" : "no ");
printf("perftsc: %s // Performance TSC\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::perftsc) ? "yes" : "no ");
printf("pcx_l2i: %s // L2I perf counter extensions\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::pcx_l2i) ? "yes" : "no ");
printf("_resv5: %s // (reserved)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_resv5) ? "yes" : "no ");
printf("_resv6: %s // (reserved)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_resv6) ? "yes" : "no ");
printf("_resv7: %s // (reserved)\n", query_cpu_feature(&info, Ecx_81_Extended_Feature_Flags::_resv7) ? "yes" : "no ");
}

int main() {
print_full_cpu_info();
}

BIN
Ver arquivo


main.cpp → tests/main.cpp Ver arquivo

@@ -1,7 +1,7 @@
#define _CRT_SECURE_NO_WARNINGS
#include <stdio.h>
#include <string.h>
#include "./types.hpp"
#include "../types.hpp"

u32 hm_hash(u32 u);
inline bool hm_objects_match(u32 a, u32 b);
@@ -12,14 +12,14 @@ inline bool hm_objects_match(Key a, Key b);
#define ZoneScoped
#define ZoneScopedN(name)

#include "./print.hpp"
#include "./testing.hpp"
#include "./bucket_allocator.hpp"
#include "./error.hpp"
#include "./hooks.hpp"
#include "./hashmap.hpp"
#include "../print.hpp"
#include "../testing.hpp"
#include "../bucket_allocator.hpp"
#include "../error.hpp"
#include "../hooks.hpp"
#include "../hashmap.hpp"

#include "./error.hpp"
#include "../error.hpp"


u32 hm_hash(u32 u) {

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